1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to a logic circuit device logically processing an input signal. More specifically, the present invention relates to a semiconductor logic circuit device correctly operating at a high speed under a low power supply voltage.
2. Description of the Background Art
In a recent large scale integrated circuit, a MOS transistor (insulated gate field effect transistor) of a component thereof is reduced in size. In order to guarantee breakdown voltage of the miniaturized MOS transistor, an operating power supply voltage is lowered. Further, the quantity of a charge/discharge current on a signal line is reduced due to the lowering of the operating power supply voltage, thereby reducing current consumption. In addition, the amplitude of an internal signal is also reduced, whereby the signal can be transmitted at a high speed to implement a high-speed operation.
When the operating power supply voltage is lowered, the MOS transistor is reduced in size and a gate insulator film is correspondingly reduced in thickness. The MOS transistor is generally reduced in size in accordance with a rule called a scaling rule. As regards a threshold voltage of the MOS transistor, however, the absolute value thereof cannot be reduced in accordance with the scaling rule together with reduction of the operating power supply voltage. The threshold voltage is a gate-to-source voltage feeding a predetermined drain current with the channel width predetermined. Even if the gate-to-source voltage Vgs is 0 V, a subthreshold current flows. This subthreshold current increases as the absolute value of the threshold voltage decreases. When the absolute value of the threshold voltage of the MOS transistor is decreased in proportion to the reduction of the power supply voltage, therefore, the subthreshold current increases to disadvantageously increase current consumption in a standby state.
In order to solve such a problem of the subthreshold leakage current, a leakage current prevention circuit called a hierarchical power supply, for example, has been proposed.
FIG. 26 illustrates the structure of a conventional semiconductor device having a hierarchical power supply structure. Referring to FIG. 26, the conventional semiconductor device includes a main power supply line 1000 transmitting a power supply voltage VCC, a main ground line 1002 transmitting a ground voltage GND, a sub power supply line 1004 coupled to the main power supply line 1000 through a switching transistor 1003, and a sub ground line 1006 coupled to the main ground line 1002 through a switching transistor 1005. The switching transistor 1003 is rendered conductive when an active cycle defining signal ZACT is active (low level), while the switching transistor 1005 is rendered conductive when an active cycle defining signal ACT is at a high level of an active state.
The semiconductor device further includes two stages of cascaded inverters 1010 and 1012 as logic circuits. Each of the inverters 1010 and 1012, which are identical in structure to each other, includes a p-channel MOS transistor PTa and an n-channel MOS transistor NTa. An input signal IN for the inverter 1010 is set low in a standby cycle (both active cycle defining signals ZACT and ACT are inactive). In the inverter 1010, the source of the p-channel MOS transistor PTa is coupled to the main power supply line 1000 while the source of the n-channel MOS transistor NTa is coupled to the sub ground line 1006. The inverter 1012 receives the voltages on the sub power supply line 1004 and the main ground line 1002 as operating power supply voltages. In such an active cycle that the input signal IN changes, the active cycle defining signals ZACT and ACT are active, the switching transistors 1003 and 1005 are rendered conductive, the sub power supply line 1004 is coupled to the main power supply line 1000, and the sub ground line 1006 is coupled to the main ground line 1002. Therefore, the voltage on the sub power supply line 1004 reaches the level of the power supply voltage VCC, and the voltage on the sub ground line 1006 reaches the level of the ground voltage GND. When the absolute values of the threshold voltages of MOS transistors PTa and NTa are decreased, the inverters 1010 and 1012 operate at a high speed to output output signals in response to the input signal IN.
In the standby cycle, the input signal IN is fixed at a low level and the output signal of the inverter 1010 is fixed at a high level. In this standby cycle, the active cycle defining signals ZACT and ACT are inactivated and hence the switching transistors 1003 and 1005 are rendered non-conductive. In the inverter 1010, the p-channel MOS transistor PTa is rendered conductive and the voltages of both the source and the drain thereof reach the level of the power supply voltage VCC. In the p-channel MOS transistor PTa, therefore, the source and drain voltages thereof reach the same voltage level to cause no leakage current. In the n-channel MOS transistor NTa of the inverter 1010, on the other hand, the gate voltage thereof is set low by the input signal IN to cause a subthreshold leakage current. At this time, the voltage level of the sub ground line 1006 rises beyond the ground voltage GND due to the leakage current. The gate-to-source voltage of the n-channel MOS transistor NTa of the inverter 1010 is set in a reverse bias state (the source voltage is higher than the gate voltage), to suppress the subthreshold leakage current.
In the inverter 1012, on the other hand, an input signal thereto is at a high level. Therefore, the p-channel MOS transistor in the inverter 1012 is rendered non-conductive to be likely to cause a leakage current (subthreshold current). However, the voltage on the sub power supply line 1004 drops below the power supply voltage VCC due to the leakage current. Also in the inverter 1012, therefore, the gate-to-source voltage of the p-channel MOS transistor is set in a reverse bias state to reduce the subthreshold current.
In the hierarchical power supply structure shown in FIG. 26, the connection manner of its power supply nodes is determined depending on the voltage level of the input signal or the output signal in the standby cycle. In this hierarchical power supply structure, therefore, connection of the power supply nodes of logic gates (inverters) can be determined if the logical level of the input signal or the output signal in the standby cycle can be predetermined. If the logical level of the input signal or the output signal in the standby cycle cannot be predicted as in random logic or the like, however, the connection path for the power supply nodes cannot be determined.
FIG. 27 illustrates an exemplary conventional random logic device. Referring to FIG. 27, this random logic device includes a drive circuit 1020 buffering input signals, a transfer circuit 1022 latching and transferring output signals of the drive circuit 1020 in synchronization with a clock signal, a logic circuit 1024 performing prescribed logical processing on output signals of the transfer circuit 1022, a transfer circuit 1026 latching and transferring output signals of the logic circuit 1024 in synchronization with the clock signal, a logic circuit 1028 performing prescribed logical processing on output signals of the transfer circuit 1026, and a transfer circuit 1030 transferring output signals of the logic circuit 1028 in synchronization with the clock signal.
The drive circuit 1020 includes drivers DR provided in correspondence to the input signals, respectively. The transfer circuit 1022 includes flip-flops F/F provided in correspondence to the drivers DR of the drive circuit 1020 respectively. The logic circuit 1024 includes logic elements GL1 to GL3 . . . . Output signals from the flip-flops F/F of the transfer circuit 1023 are transferred to the logic elements GL1 to GL3 . . . of the logic circuit 1024 respectively. Connection paths between the flip-flops F/F and the logic elements GL1 to GL3 are determined in accordance with the logical processing performed in practice.
The transfer circuits 1026 includes flip-flops F/F provided in correspondence to the logic elements GL1 to GL3 . . . of the logic circuit 1024 respectively. Two flip-flops F/F are provided for transferring complementary signals with respect to each logic element GLi (i=1 to 3 . . . ).
The logic circuit 1028 includes logic elements GL4 to GL6 performing logical processing in parallel. The logic elements GL4 to GL6 . . . receive prescribed output signals from the flip-flops F/F of the transfer circuit 1026.
The transfer circuit 1030 includes flip-flops F/F provided in correspondence to the logic elements GL4 to GL6 . . . , Also in the transfer circuit 1030, two flip-flops F/F are provided for each logic element GLj (j=4 to 6 . . . ) of the logic circuit 1028, to transfer complementary signals.
The random logic device shown in FIG. 27 is such a synchronous logic device that the logic circuits 1020 and 1028 statically perform logical processing respectively and the transfer circuits 1022 and 1026 transfer signals in synchronization with the clock signal. The logical levels of the output signals of the logic circuits 1024 and 1028 vary with the signals inputted from the drive circuit 1020. In particular, the voltage levels (logical levels) of the signals latched in the transfer circuits 1022, 1026 and 1030 vary with the output signals from the corresponding logic elements, and hence the hierarchical power supply structure shown in FIG. 26 cannot be applied to the transfer circuits 1022, 1026 and 1030. This also applies to the logic circuits 1024 and 1028.
FIG. 28 illustrates an exemplary structure of each flip-flop F/F shown in FIG. 27. Referring to FIG. 28, the flip-flop F/F includes a clocked inverter 1032 activated, when a clock signal CKB is at a high level, to invert and output the input signal, an inverter 1034 inverting the output signal of the clocked inverter 1032, a clocked inverter 1036 activated, when a clock signal CK is at a high level, for inverting an output signal of the inverter 1034 and transmitting the inverted signal to an input of the inverter 1034, a transmission gate 1038 transmitting the output signal of the inverter 1034 in accordance with clock signal CK, an inverter 1040 inverting the output signal of the transmission gate 1038, a clocked inverter 1042, activated when the clock signal CKB is at a high level, for inverting an output signal of the inverter 1040 and transmitting the inverted signal to an input of the inverter 1040, and an inverter 1044 inverting and outputting the output signal of the inverter 1040.
The clock signals CK and CKB are complementary clock signals. When the clock signal CK is at a high level, the clocked inverters 1032 and 1042 are set in an output high impedance state, while the transmission gate 1038 is rendered conductive. Further, the clocked inverter 1036 operates as an inverter. In this state, therefore, the inverters 1034 and 1036 latch the signal, which in turn is transmitted to the inverter 1040 through the transmission gate 1038. The output signal of the inverter 1040 is outputted through the inverter 1044.
When the clock signal CK goes low, the clocked inverter 1036 enters an output high impedance state, the clocked inverters 1032 and 1042 operate as inverters, and the transmission gate 1038 is rendered non-conductive. Therefore, the inverters 1040 and 1042 form a latch circuit, to latch and output the signal supplied in the high-level state of the clock signal CK. On the other hand, the clocked inverter 1032 inverts the input signal and supplies the inverted signal to the inverter 1034. The transmission gate 1038 is non-conductive and hence the output signal of the inverter 1034 simply changes in response to the input signal.
The flip-flop F/F shown in FIG. 28 takes and transfers the supplied signal in accordance with the two-phase clock signals CK and CKB. When the definite timings for the output signals of the logic circuits 1020 and 1028 shown in FIG. 27 are different from each other, therefore, the signals can be sequentially transferred in accordance with the clock signals CK and CKB for performing logical processing in synchronization with the clock signals.
As shown in FIG. 28, however, the logical level of the output signal from each inverter of the flip-flop F/F varies with the input signal, and cannot be predicted. Therefore, the hierarchical power supply structure shown in FIG. 26 cannot be applied for reducing current consumption in the flip-flop F/F in the standby cycle.
Not only in the standby cycle in a normal operating mode but also in a sleep mode set when no logical processing is performed over a long period, a similar problem arises to prevent reduction of current consumption.
In order to reduce current consumption in the standby cycle and in the sleep mode or a power down mode in the aforementioned random logic device, there has been also proposed a method of separately providing a nonvolatile memory circuit called a balloon circuit for saving information to be held and cutting off the power supply for a main circuit in the standby cycle or the sleep mode (refer to IEEE JSSC Vol. 30, No. 8, 1995).
This structure cuts off the power supply and hence no path is present for feeding a current. Thus, current consumption in the logic elements and the flip-flops can be eliminated.
However, the balloon circuit must be provided independently of signal paths performing general logical processing for saving the information through another signal path, and hence the occupying area increases and control for saving the information is complicated.
Such a random logic device is not restricted to a general logical processing circuit. When an equipment called PDA (personal digital assistants: portable information terminal equipment), for example, is not used over a long period, its internal circuit is set in a sleep mode to prepare for next processing. In such a portable equipment driven by a battery, the current dissipation must be minimized in the sleep mode.
An object of the present invention is to provide a semiconductor circuit device capable of reducing current consumption under a low power supply voltage without deteriorating high-speed operability.
The semiconductor circuit device according to the present invention includes a pass transistor logic element formed by a pass transistor passing a supplied signal for performing prescribed logical processing on an input signal for outputting and a first latch circuit having an amplifier stage receiving the output signal of the pass transistor logic element with a high input impedance for amplification and a latch stage coupled with the amplifier stage for latching an output signal thereof.
A circuit part performing actual logical processing is formed by the pass transistors, and the pass transistor logic simply transmits the signal to consume no power supply voltage. Thus, the logic element can be implemented with a MOS transistor having a low threshold voltage so that the logic part can be driven at a high speed with low current consumption.
The output signal of the pass transistor logic element is supplied to the latch circuit having a high input impedance, whereby no leakage current flows from the pass transistor logic element to a power supply node, and low current consumption is implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.